Recently static RAMs employing an automatic power-down system have been developed which make word lines and sense amplifiers inoperative after completion of a series of read operations by use of an address signal change detection signal. Examples of such static RAMs include devices "HM62256, HM628128" marketed by Hitachi, Ltd.
The automatic power-down system described above makes word lines and sense amplifiers inoperative at the time of completion of a data read operation even if a chip select signal CS or the like is under the low level active state, and thereby reduces current consumption. However, since the automatic power-down function operates even in an acceleration test such as aging, the actual operation time of an internal circuit becomes shorter than the test cycle of the acceleration test. This results in the problem that the time necessary for the acceleration test becomes extended.
It is an object of the present invention to provide a static RAM which can shorten the test time of such an acceleration test while still accomplishing the low power consumption advantages of an automatic power-down system in an ordinary operation mode.
The abov and other objects and novel features of the present invention will become more apparent from the following detailed description in conjunction with the accompanying drawings.